Dynamic Random Access Memory utilizes capacitors to store bits of information within an integrated circuit. A capacitor is formed by placing a dielectric material between two electrodes formed from conductive materials. A capacitor's ability to hold electrical charge (i.e., capacitance) is a function of the surface area of the capacitor plates A, the distance between the capacitor plates d (i.e. the physical thickness of the dielectric layer), and the relative dielectric constant or k-value of the dielectric material. The capacitance is given by:
                    C        =                  κ          ⁢                                          ⁢                      ɛ            o                    ⁢                      A            d                                              (                  Eqn          .                                          ⁢          1                )            where ∈o represents the vacuum permittivity.
The dielectric constant is a measure of a material's polarizability. Therefore, the higher the dielectric constant of a material, the more charge the capacitor can hold. Therefore, if the k-value of the dielectric is increased, the area of the capacitor can be decreased and maintain the desired cell capacitance. Reducing the size of capacitors within the device is important for the miniaturization of integrated circuits. This allows the packing of millions (mega-bit (Mb)) or billions (giga-bit (Gb)) of memory cells into a single semiconductor device. The goal is to maintain a large cell capacitance (generally ˜10 to 25 fF) and a low leakage current (generally <10−7 A cm−2). The physical thickness of the dielectric layers in DRAM capacitors could not be reduced unlimitedly in order to avoid leakage current caused by tunneling mechanisms which exponentially increases as the thickness of the dielectric layer decreases.
Traditionally, SiO2 has been used as the dielectric material and semiconducting materials (semiconductor-insulator-semiconductor [SIS] cell designs) have been used as the electrodes. The cell capacitance was maintained by increasing the area of the capacitor using very complex capacitor morphologies while also decreasing the thickness of the SiO2 dielectric layer. Increases of the leakage current above the desired specifications have demanded the development of new capacitor geometries, new electrode materials, and new dielectric materials. Cell designs have migrated to metal-insulator-semiconductor (MIS) and now to metal-insulator-metal (MIM) cell designs for higher performance.
One class of high k dielectric materials possessing the characteristics required for implementation in advanced DRAM capacitors are high k metal oxide materials. Examples of suitable dielectric materials comprise SiO2, a bilayer of SiO2 and SixNy, SiON, Al2O3, HfO2, HfSiOx, ZrO2, Ta2O5, TiO2, Nb2O5, SrTiO3 (STO), BaSrTiOx (BST), PbZrTiOx (PZT), etc. TiO2 and ZrO2 are two specific examples of metal oxide dielectric materials which display significant promise in terms of serving as a high k dielectric material for implementation in DRAM capacitors.
Typically, DRAM devices at technology nodes of 80 nm and below use MIM capacitors wherein the electrode materials are metals. These electrode materials generally have higher conductivities than the semiconductor electrode materials, higher work functions, exhibit improved stability over the semiconductor electrode materials, and exhibit reduced depletion effects. The electrode materials must have high conductivity to ensure fast device speeds. Representative examples of electrode materials for MIM capacitors are metals, conductive metal oxides, conductive metal silicides, conductive metal nitrides (i.e. TiN), or combinations thereof. MIM capacitors in these DRAM applications utilize insulating materials having a dielectric constant, or k-value, significantly higher than that of SiO2 (k=3.9). For DRAM capacitors, the goal is to utilize dielectric materials with k values greater than about 40. Such materials are generally classified as high k materials. Representative examples of high k materials for MIM capacitors are non-conducting metal oxides, non-conducting metal nitrides, non-conducting metal silicates or combinations thereof. These dielectrics may also include additional dopant materials.
A figure of merit in DRAM technology is the electrical performance of the dielectric material as compared to SiO2 known as the Equivalent Oxide Thickness (EOT). A high k material's EOT is calculated using a normalized measure of silicon dioxide (SiO2 k=3.9) as a reference, given by:
                    EOT        =                              3.9            κ                    ·          d                                    (                  Eqn          .                                          ⁢          2                )            where d represents the physical thickness of the capacitor dielectric.
As DRAM technologies scale below the 40 nm technology node, manufacturers must reduce the EOT of the high k dielectric films in MIM capacitors in order to increase charge storage capacity. The goal is to utilize dielectric materials that exhibit an EOT of less than about 0.8 nm while maintaining a physical thickness of about 5-20 nm.
Generally, as the dielectric constant of a material increases, the band gap of the material decreases. For example. The rutile phase of TiO2 has a k-value of about 80 and a band gap of about 3.0 eV while ZrO2 in the tetragonal phase has a k-value of about 43 and a band gap of about 5.8 eV. The low band gap may lead to high leakage current in the device. As a result, without the utilization of countervailing measures, capacitor stacks implementing high k dielectric materials may experience large leakage currents. High work function electrodes (e.g., electrodes having a work function of greater than 5.0 eV) may be utilized in order to counter the effects of implementing a reduced band gap high k dielectric layer within the DRAM capacitor. Metals, such as platinum, gold, ruthenium, and ruthenium oxide are examples of high work function electrode materials suitable for inhibiting device leakage in a DRAM capacitor having a high k dielectric layer. The noble metal systems, however, are prohibitively expensive when employed in a mass production context. Moreover, electrodes fabricated from noble metals often suffer from poor manufacturing qualities, such as surface roughness, poor adhesion, and form a contamination risk in the fab.
Conductive metal oxides, conductive metal silicides, conductive metal nitrides, or combinations thereof comprise other classes of materials that may be suitable as DRAM capacitor electrodes. Generally, transition metals and their conductive binary compounds form good candidates as electrode materials. The transition metals exist in several oxidation states. Therefore, a wide variety of compounds are possible. Different compounds may have different crystal structures, electrical properties, etc. It is important to utilize the proper compound for the desired application.
In one example, molybdenum has several binary oxides of which MoO2 and MoO3 are two examples. These two oxides of molybdenum have different properties. MoO2 has shown great promise as an electrode material in DRAM capacitors. MoO2 has a distorted rutile crystal structure and serves as an acceptable template to promote the deposition of the rutile-phase of TiO2 as discussed above. MoO2 also has a high work function (can be >5.0 eV depending on process history) which helps to minimize the leakage current of the DRAM device. However, oxygen-rich phases (MoO2+x) degrade the performance of the MoO2 electrode because they do not promote the deposition of the rutile-phase of TiO2 and have higher resistivity than MoO2. For example, MoO3 (the most oxygen-rich phase) has an orthorhombic crystal structure and is a dielectric.
Generally, a deposited thin film may be amorphous, crystalline, or a mixture thereof. Furthermore, several different crystalline phases may exist. Therefore, processes (both deposition and post-treatment) must be developed to maximize the formation of crystalline MoO2 and to minimize the presence of MoO2+x phases. Deposition processes and post-treatment processes in a reducing atmosphere have been developed that allow crystalline MoO2 to be used as the first electrode (i.e. bottom electrode) in DRAM MIM capacitors with TiO2 or doped-TiO2 high k dielectric materials. Examples of the post-treatment process are further described in U.S. application Ser. No. 13/084,666 filed on Apr. 12, 2011, entitled “METHOD FOR FABRICATING A DRAM CAPACITOR” which is incorporated herein by reference. However, these DRAM MIM capacitors have continued to use noble metal (i.e. Ru) materials for the second electrode (i.e. top electrode).
After the formation of the second electrode, the capacitor stack is then subjected to a post metallization anneal (PMA) treatment. The PMA treatment serves to crystallize the second electrode and to anneal defects in the dielectric and interface states that are formed at the dielectric/second electrode interface during the deposition. Also, if there is no post dielectric anneal (PDA) treatment done before metallization, the PMA treatment can serve to crystallize the dielectric layer to improve the k value and fill oxygen vacancies. Examples of the PDA and PMA treatments are further described in U.S. application Ser. No. 13/159,842 filed on Jun. 14, 2011, entitled “METHOD OF PROCESSING MIM CAPACITORS TO REDUCE LEAKAGE CURRENT” and is incorporated herein by reference. As discussed above, MoO2 is sensitive to oxidation to form oxygen-rich compounds that negatively impacts its performance as an electrode material. The reducing atmosphere anneal processes discussed previously with respect to the use of crystalline MoO2 as a first electrode are not an option at this stage of the device manufacture because they would degrade the performance of the dielectric layer through the formation of oxygen vacancies. TiO2 high k dielectric materials are especially sensitive to processing conditions and increases in the leakage current are observed, likely due to the formation of oxygen vacancies.
At some DRAM device nodes, TiN may be used as the first electrode. TiN may be used with ZrO2 dielectric layers because the high k tetragonal phase of ZrO2 forms easily on TiN. The oxygen moiety within the ZrO2 layer is reasonably stable and the concentration of oxygen vacancies is low. This contributes to the low leakage current observed for ZrO2 dielectric layers. However, since the k-value is lower than desired (k<˜43), the EOT is too large for next generation DRAM technologies. As an example, ZrO2 MIM capacitors can have leakage currents in the range of about 8×10−8 A/cm2 at an EOT of about 0.70 nm to about 1.5×10−8 A/cm2 at an EOT of about 0.85 nm. The EOT target for next generation DRAM technologies is less than about 0.60 nm. In the case of ZrO2 dielectric layers, TiN is typically used as the second electrode as well.
As discussed previously, the rutile phase of TiO2 is an attractive candidate high k dielectric material with a k-value in excess of about 80 depending on processing conditions. The high k-value should allow the formation of MIM capacitor stacks with low EOT values within the physical thickness constraints of advanced DRAM technologies. The use of crystalline MoO2 would be attractive as a first electrode since it would serve as a good template to promote the formation of the rutile phase of TiO2. Ideally, the crystalline MoO2 would be used as the second electrode as well to form a symmetric MIM stack. However, currently Ru is used for the second electrode due to integration issues surrounding the use of MoO2 as the second electrode. As discussed previously, both MoO2 and TiO2 are very sensitive to the environment used during the various annealing steps. The oxidation of MoO2 to MoO2+x and the loss of oxygen in TiO2 to form oxygen vacancies both contribute to the higher leakage current observed in MIM stacks using these materials. As an example, TiO2 MIM capacitors can have leakage currents in the range of about 8×10−6 A/cm2 at an EOT of about 0.38 nm to about 1.0×10−7 A/cm2 at an EOT of about 0.50 nm.
Therefore, there is a need to develop methods for forming capacitor stacks that combine the low leakage current and simple integration processes of ZrO2 based dielectric layers with the high k and low EOT benefits of TiO2 based dielectric layers.